We are developing a novel optical interconnect for interfacing with the brain and seeking an IC Layout Design engineer to work on the physical assembly and verification of our analog, digital, and mixed-signal blocks, IPs and ASICs.

Role & responsibilities:

• Design the layout of analog, digital, and mixed-signal IP blocks. Work closely with the circuit designers to identify layout constraints and identify critical and sensitive active and passive devices in the schematics / netlist.
• Define the floor plan of the circuit in terms of device placement, power, and signal routing. For analog and mixed-signal blocks, you will be asked to do manual placement and routing of the block to achieve compactness.
• Perform detailed physical checks, including Design Rule Checks (DRCs) for regular core, full-chip, antenna, and density rules, using industry standard tools.
• Perform Layout-versus-Schematics (LVS) checks on the layouts using industry standard tools. Follow a systematic approach to debug connectivity and routing issues, to be able to debug and solve LVS issues efficiently at IP and full-chip levels.
• Perform parasitics extraction on layouts. Report extracted parasitics in an efficient way, and discuss with circuit designers if a layout iteration will be needed or not.
• Create extracted views for the layouts to be used for post-layout simulations and verifications. In most of the cases, it will be preferred if you could run quick extracted circuit simulations to be able to close on the layout constraints quickly.
• Develop electrical models for the power/ground grid and signal busses using PDK materials to perform IR drop and signal integrity analyses at IP and full-chip level.
• Automate repeated layout tasks using scripting and programming languages, such as skill or python.

Key qualifications:

• 2+ years of industrial experience on the layout design and physical implementation of analog and mixed-signal CMOS IPs from specification to GDS.
• Solid understanding of CMOS analog and digital circuits at transistor level is a must.
• Solid understanding of digital CMOS VLSI design is required.
• Experience in mixed-signal CMOS technologies (180nm or finer geometries) in terms of schematic and layout design is required.
• Experienced user of industry standard commercial IC Layout Editors is required
• Experienced user of industry standard commercial DRC/LVS/Extraction tools is required

Preferred qualifications:

• Experience in Cadence IC Design Tools, such as Virtuoso Schematic and Layout Editors, PVS DRC/LVS, Quantus Extraction, Spectre Circuit Simulator is preferred
• Experience in Calibre DRC/LVS/Extraction tools from Siemens is preferred
• Experience in open-source IC design, simulation, and physical verification tools and flows is preferred
• Good command of programming / scripting languages such as skill or python to automate repeated layout and schematic tasks is a plus
• Having a track record of successful layout IP creation that entered into fabricated chips is a big plus

Salary/Pay Range:

For individuals hired to work in California, Science is required by law to include a reasonable estimate of the compensation range for this role. We determine your level based on your interview performance and make an offer based on geo-located salary bands. The base salary range for this full-time position is $100,000 - $150,000 + equity + benefits. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Please keep in mind that the equity portion of the offer is not included in these numbers.

Benefits:

At Science, our benefits are in place to support the whole you:

• Competitive salary and equity
• Medical, dental, vision and life insurance
• Flexible vacation and company-paid holidays
• Healthy meals and snacks provided
• Paid parental, jury duty, bereavement, family care and medical leave
• Dependent Care Flexible Spending Account, subsidized by Science
• Flexible Spending Account
• 401(k)