We are developing a novel optical interconnect for interfacing with the brain and seeking a Mixed-Signal IC Design Engineer to work in the design and verification of analog and digital building blocks of mixed-signal IPs and ASICs.

Role Responsibilities

• Design analog, digital, and mixed signal CMOS circuits at transistor level
• Perform performance optimization to achieve low-power, low-noise, improved signal quality, and small implementation area
• Develop detailed simulation and verification plans using analog and mixed-signal circuit simulators and automate the flow from specification to compliance
• Perform detailed floor planning and design the layout for designed IPs and ASICs
• Run physical verifications (DRC, LVS, Extraction) for the IPs designed making them ready to be used in the tapeouts
• Perform full-chip transistor level versifications of the analog and mixed-signal ASICs before tapeout
• Prepare checklist for tapeouts, automate them, and use them for tapeouts
• Prepare detailed documentations for the designed IPs and chips, such as test plans, user’s manuals, and product datasheets.

Key qualifications:

• 4+ years experience in the design and verification of analog and mixed-signal IPs and ASICs using commercial IC Design Tools, using modern deep-submicron CMOS mixed-signal technologies
• Solid understanding of analog, digital, and mixed-signal CMOS circuit design at transistor level
• Strong background on low-noise and low-power analog and mixed-signal design
• Experience in the design and modelling of analog building blocks, such as bandgap voltage references, voltage and current mode DACs, and ADCs, low-noise amplifiers (LNAs), PLLS, DLLs, differential I/O circuits
• Experience in full-chip transistor level simulation using fast-Spice simulators used in the industry
• Simulation and verification of CMOS logic gates and digital circuits using Spice and Verilog simulators
• Familiarity with CMOS, LVDS, CML type IO devices, and simulating and modeling them at Spice and IBIS level
• MSc or PhD in Electrical Engineering

Preferred qualifications:

• Experience in die and wafer level probing and chip-bring-up procedures and familiarity with standard lab test equipment
• Familiarity with FPGA programming for chip testing and characterization
• Good command on scripting languages (such as Python, TCL, or Perl) to automate design and test procedures, and analyze / visualize results

Salary/Pay Range:

For individuals hired to work in California, Science is required by law to include a reasonable estimate of the compensation range for this role. We determine your level based on your interview performance and make an offer based on geo-located salary bands. The base salary range for this full-time position is $140,000 – $230,000 + equity + benefits. Within the range, individual pay is determined by several factors, including job-related skills, experience, and relevant education or training. Please keep in mind that the equity portion of the offer is not included in these numbers.

Benefits:

At Science, our benefits are in place to support the whole you:

• Competitive salary and equity
• Medical, dental, vision and life insurance
• Flexible vacation and company-paid holidays
• Healthy meals and snacks provided onsite
• Paid parental, jury duty, bereavement, family care and medical leave
• Dependent Care Flexible Spending Account, subsidized by Science
• Flexible Spending Account
• 401(k)